FACE-Module Design: PCIe and PEG lane configuration

Post Reply
sonnenfl
Posts: 10
Joined: Thu Oct 11, 2012 11:48 am

FACE-Module Design: PCIe and PEG lane configuration

Post by sonnenfl »

Hello,
I'm designing a FACE module and want to use the PCIe lanes on the FACE module connectors.

This picture shows an x8 and x2 link from the CPU to the FACE module and two x1 links from the System Controller Hub to the FACE module.

Which pins on the FACE module connector are connected to the CPU?
Are those the "PEG" lanes on FACE connector #2?

Do I need to do something with the DGPU_* signals on connector #2?
(I will not connect a GPU to the PEG lanes but an FPGA used as frame grabber)

Which of the lanes on FACE connector #1 are the x1 lanes and which ones are the x2 lane?
Or can I assign them like I want?

-- Florian

gabrielh
Site Admin
Posts: 1260
Joined: Thu Jun 02, 2011 1:13 pm

Re: FACE-Module Design: PCIe and PEG lane configuration

Post by gabrielh »

Hello Florian

Please refer to this wiki http://www.fit-pc.com/wiki/index.php/FA ... umentation for the detailed information about FACE module custom design
Gabriel Heifets

Fit-PC2/3/IntensePC support.

sonnenfl
Posts: 10
Joined: Thu Oct 11, 2012 11:48 am

Re: FACE-Module Design: PCIe and PEG lane configuration

Post by sonnenfl »

I should have mentioned that I have already looked at those documents and the questions I asked are the things I could not find in the documentation.

By the way, the "Face Module Design Guide" is outdated. There were some additions from Fit-PC 3 to Intense-PC that are not mentioned in the PDF. (Like those PCIe lanes I mentioned or the LVDS port)

So, my questions still stand...

-- Florian

gabrielh
Site Admin
Posts: 1260
Joined: Thu Jun 02, 2011 1:13 pm

Re: FACE-Module Design: PCIe and PEG lane configuration

Post by gabrielh »

Dear Florian

PCIE_TXP8_EXT
PCIE_TXN8_EXT
PCIE_RXN8_EXT
PCIE_RXP8_EXT
IT'S X1 Line that is coming from chipset

PCIE_TXP7_EXT
PCIE_TXN7_EXT
PCIE_RXN7_EXT
PCIE_RXP7_EXT
IT'S X1 Line that is coming from chipset

PCIE_TXP1_C
PCIE_RXP1_C
PCIE_RXP1_SLOT1
PCIE_TXP1_SLOT1

relevant clock CLK_PCIE_P7, CLK_PCIE_N7



PEG_TXP7
PEG_TXN7
PEG_RXP7
PEG_RXN7

IT'S X2 Line that that is coming from CPU

PEG_RXP8 - PEG_RXP15

IT'S X8 Line that that is coming CPU
Gabriel Heifets

Fit-PC2/3/IntensePC support.

sonnenfl
Posts: 10
Joined: Thu Oct 11, 2012 11:48 am

Re: FACE-Module Design: PCIe and PEG lane configuration

Post by sonnenfl »

Hello Gabriel,

I cannot find those signal names in the "FACE Module Design Guide" or in the schematics that come with the "FACE Module Design Package".
The naming is completely different. (Maybe you gave me names used in internal documentation?)

Here is a screenshot of the pin layout of the connectors in the "FM-XTD reference design":

Image


Can you rewrite your answer with these signal names, please?

-- Florian

gabrielh
Site Admin
Posts: 1260
Joined: Thu Jun 02, 2011 1:13 pm

Re: FACE-Module Design: PCIe and PEG lane configuration

Post by gabrielh »

CPU -> PEG x8 AND PEG x1
CHIPSET -> 3 PCIe x1 (1,7,8)

CPU PEG x8 :
P2 A1-A24,B1-B24 RELEVANT CLOCK P2-B26,B27
PEG_RX/TX0 - PEG_RX/TX7

CPU PEG x1 :
P1-B44,B45 A44,A45 (PCIe 0)

CHIPSET -> 3 PCIe x1 (1,7,8)
P1-A35,36 B35,36 (PCIe 3)
P1-A38,39 B38,39 (PCIe 2)
P1-A41,42 B41,42 (PCIe 1)

CLOCK : P1- B32,B33
Gabriel Heifets

Fit-PC2/3/IntensePC support.

Post Reply

Return to “General FACE Module questions”